1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus that is capable of reading out an output from a light receiving pixel in a given area on the light receiving surface of the pickup apparatus.
2. Description of the Related Art
A solid-state image pickup apparatus capable of reading a light receiving pixel in a given area on the light receiving surface is disclosed, for example, in Japanese Unexamined Patent Publication No. 4-277985. In this disclosure, a shift register constituting scan means for sequentially reading out the output from each light receiving pixel is divided into a plurality of blocks, and the output from the light receiving pixels corresponding to a divided block is read. In this method, however, the unit of repetition of the shift register is the divided block. The quality of the signal derived from the border between blocks may suffer variations. The selection of the area to be read is possible only by the unit of block that is predetermined at the stage of fabrication of the solid-state image pickup apparatus. Therefore, it is impossible to readout an output from a light receiving pixel in an arbitrary area on the light receiving surface.
The inventors of this invention have proposed a scanning circuit in Japanese Unexamined Patent Publication No. 6-35093 which resolves the above problems. FIG. 1 is the schematic diagram of that scanning circuit. The constitution of this scanning circuit is first discussed. Designated 101 is a shift register unit constructed of a first clocked inverter 101-1 and a second clocked inverter 101-2 cascaded, and a shift register is constructed of a plurality of shift register units cascaded. There are shown further a memory switch 102, a transfer switch 103, and a memory unit 104 constructed of a first inverter 104-1 and a second inverter 104-2 in series connection. The output node of the first clocked inverter 101-1 is connected to one terminal of the memory switch 102 and one terminal of the transfer switch 103. The other terminal of the memory switch 102 is connected to the input terminal of the first inverter 104-1 of the memory unit 104. The output terminal of the second inverter 104-2 of the memory unit 104 is connected to the other terminal of the transfer switch 103. A plurality of unit stages 106 of the scanning circuit are cascaded to form the scanning circuit. FIG. 1 shows the scanning circuit that is made up of 7 unit stages. The scanning circuit in the solid-state image pickup apparatus includes a lot more unit stages in practice.
The first clocked inverter 101-1 becomes active when a driving clock .phi.2 is at a high level, and the second clocked inverter 101-2 becomes active when a driving clock .phi.1 is at a high level. An input clock .phi.ST is fed to the input terminal of the shift register unit 101 at the first unit stage. The memory switch 102 goes conductive when a clock .phi.TBA is at a high level, and the transfer switch 103 goes conductive when a clock .phi.LD is at a high level.
As can be seen from the timing diagram in FIG. 4 that will be referred to for the description of the operation of an embodiment 1 of the present invention, the scanning circuit thus constructed sequentially transfers the clock .phi.ST to nodes SR 1.0, SR 2.0, SR 3.0, SR 4.0, SR 5.0. SR 6.0, and SR 7.0 in synchronism with the clocks .phi.1 and .phi.2 when the clocks .phi.1 and .phi.2 and clock .phi.ST are fed with the clocks .phi.TBA and .phi.LD kept at a low level. Also as can be seen from the timing diagram in FIG. 5 in connection with the operation of the embodiment 1, a level at each of nodes SR 0.5, SR 1.5, SR 1.5 and SR 3.5 is stored at memory units 104 by driving the clock .phi.TBA high at the same timing as the clock .phi.2 at time t.sub.TB
By driving the clock .phi.LD high at the same timing as the clock .phi.1 at time t.sub.LD, levels stored at time t.sub.TB are transferred to nodes SR 0.5, SR 1.5, SR 2.5, and SR 3.5. Since the clock .phi.1 is high level, the signals at nodes SR 0.5, SR 1.5, SR 2.5, SR 3.5, SR 4.5, SR 5.5, and SR 6.5 are output in their inverted forms to nodes SR 1.0, SR 2.0, SR 3.0, SR 4.0, SR 5.0, SR 6.0, and SR 7.0, respectively. The high level input of .phi.ST that has been fed at time t.sub.ST sequentially appears at SR 3.0 and subsequent nodes from time t.sub.LD thereafter. This means that the scanning of the shift register starts at node SR 3.0.
The disadvantage of the scanning circuit in FIG. 1 is now discussed. The memory unit 104 in the scanning circuit in FIG. 1 is constructed of inverters only. When the memory switch 102 remains nonconductive for a long period of time, the potential (voltage) at the input terminal of the inverter 104-1 becomes unstable due to leaks or other causes. If the voltage shifts to an intermediate level between a power supply voltage VDD and VSS, a current flows through the inverter 104-1 increasing power consumption. Since the voltage at the output of the inverter 104-1 remains unstable, the inverter 104-2 also behaves in a similar fashion. When under such a condition, data is transferred to the shift register unit 101 from the memory unit 104, data different from the original data stored in the memory unit 104 can be transferred to the shift register unit 101, and the shift register can malfunction.
When the readout of the signal starts at an arbitrary position and ends at another arbitrary position, OB (optical black) clamping is rendered inoperable if a light shielding pixel is not included within the range of the signal readout. Thus, a reliable image pickup operation cannot be executed.